The present invention relates to methods for the formation of zero marks on semiconductor devices.
Zero marks facilitate alignment of layers in semiconductor devices. They can be located on the periphery of the device or, alternatively, in every diode field. Typically, the zero marks are formed first and are carried along during further structure formation.
In FIGS. 1(a)-1(d) is shown a traditional approach to the formation of zero marks and isolation structures. First, an oxide layer 104 is formed on a silicon substrate 102. Then, a first photoresist 106 layer is spun on the surface of the oxide layer 104, resulting in the structure shown in FIG. 1(a).
Next, the first photoresist layer 106 is patterned to form a zero marks mask. Afterwards, an etch is performed through the exposed portions of the oxide layer 104 and into the silicon substrate 102 to form a set of zero marks 108, as shown in FIG. 1(b).
The first photoresist layer 106 is then stripped, and a second photoresist layer 110 is spun over the surface of the structure and patterned to form a deep well mask. Subsequently, an etch is performed to remove the exposed portions of the oxide layer 104 and form a photomasking xe2x80x9cholexe2x80x9d 112 over the active region, illustrated in FIG. 1(c). Unlike the prior etch to form the zero marks 108, the silicon substrate 102 is not typically penetrated.
Ion implantation is then performed over the photomasking xe2x80x9cholexe2x80x9d to form a deep P or N well 114, as shown in FIG. 1(d). Finally, the second photoresist layer 110 is stripped and the surface is cleaned, to form the structure shown in FIG. 1(e).
In one aspect, the present invention concerns a method for making a semiconductor structure, comprising patterning a photoresist layer to form both a zero marks pattern and a well implant mask pattern. The photoresist layer is on a region of a substrate.
In a second aspect, the present invention is a semiconductor structure, comprising a substrate and a photoresist layer on a region of the substrate. The photoresist layer has been patterned to form both a zero marks pattern and a deep well mask pattern.
The term xe2x80x9csubstratexe2x80x9d refers to any semiconductor material conventionally known to those of ordinary skill in the art. Examples include silicon, gallium arsenide, germanium, gallium nitride, aluminum phosphide, and alloys such as Si1xe2x88x92xGex and AlxGa1xe2x88x92xAs, where 0xe2x89xa6xc3x97xe2x89xa61. Many others are known, such as those listed in Semiconductor Device Fundamentals, on page 4, Table 1.1 (Robert F. Pierret, Addison-Wesley, 1996). Preferably, the semiconductor substrate is silicon, which may be doped or undoped.
The term xe2x80x9coxidexe2x80x9d refers to a metal oxide conventionally used to isolate electrically active structures in an integrated circuit from each other, typically an oxide of silicon and/or aluminum (e.g., SiO2 or Al2O3, which may be conventionally doped with fluorine, boron, phosphorus or a mixture thereof, preferably SiO2 or SiO2 conventionally doped with 1-12 wt % of phosphorous and 0-8 wt % of boron).
The term xe2x80x9cdielectric layerxe2x80x9d refers to any dielectric material conventionally known to those of ordinary skill in the art. Examples include conventional oxides, nitrides, oxynitrides, and other dielectrics, such as borophosphosilicate glass (BPSG), borosilicate glass (BSG), phosphosilicate glass, spin-on glass (SOG), silicon oxide, P-doped silicon oxide (P-glass), and silicon nitride, for example SiO2, Si3N4, Al2O3, SiOxNy, etc. When the dielectric layer is an oxide layer, it preferably has a thickness of 10 to 999 xc3x85, more preferably a thickness of 100 to 300 xc3x85.